Exemplary embodiments of the present invention relate to a nonvolatile memory device, and more particularly, to a nonvolatile memory device and a method for fabricating the same.
In a three-dimensional nonvolatile memory device, a U-shaped string structure is a structure in which a source selection gate and a drain selection gate are formed over a memory string. It is known that the U-shaped string structure is very advantageous in view of device characteristics, as compared with a vertical string structure in which selection gates are formed above and under a memory string. To operate the U-shaped memory string, a transistor for electrical coupling is required at the bottom. Such a transistor is called a pipe channel transistor.
Two strings coupled to a source and a drain are coupled by a pipe channel transistor. In addition, control gate electrodes of two strings must be separated from each other by an etching process.
FIG. 1 is a cross-sectional view of a conventional nonvolatile memory device.
Referring to FIG. 1, a pipe gate 12 is formed on a bottom substrate 11. A first string MS1 and a second string MS2 are formed on the pipe gate 12. The first string MS1 and the second string MS2 are coupled together by a pipe channel 17A to thereby constitute a single memory string.
The first string MS1 and the second string MS2 include a cell stack in which first insulation layers 13 and control gate electrodes 14 are alternately stacked several times. The cell stack and the pipe gate 12 are etched to form a cell channel hole 15 and a pipe channel hole 12A. Due to the cell channel hole 15 and the pipe channel hole 12A, the two strings have a U-shaped string structure. A charge storage or charge trapping layer 16, a cell channel 17, and a second insulation layer 18 are buried in the cell channel hole 15. The charge storage or charge trapping layer 16 includes a blocking layer, a charge trap layer, and a tunnel insulation layer which are sequentially stacked. The cell channel 17 has a pair of columnar structures. The pipe channel 17A couples the bottoms of a pair of cell channels 17. The control gate electrodes 14 of the first string MS1 and the control gate electrodes 14 of the second string MS2 are separated from each other by a slit 19.
In the conventional nonvolatile memory device of FIG. 1, the number of layers of the cell stack must increase in order to increase cell intensity. However, as the number of layers of the cell stack increases, it becomes more difficult to apply a contact etching process and a slit etching process for forming the slit 19. In particular, in the case of the slit etching process, the damage 20 of the pipe gate 12 should ideally be prevented.
However, as the number of layers of the cell stack increases, it is likely that the pipe gate 12 is damaged as indicated by reference numeral 20.
In order to address this concern, a passivation layer may be formed on the pipe gate 12 upon the etching of the cell stack. In this case, however, the gap between the lowermost control gate electrode 14 and the pipe gate 12 increases, thereby lowering the current supplied when a cell is in an “on” state.